The research and development work in the SystemDesign laboratory focuses on the application of effective and systematic methods for designing and verifying electronic circuits, e.g. in the form of assemblies, microcomputers, application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs).

Research areas:

• Design and application of microelectronic components and systems for image processing, signal processing, and microsystems technology.
• Description languages (VHDL, SystemVerilog, SystemC, VHDL-AMS)
• Simulation and verification of electronic systems
• Standard cell design and FPGA implementations using CAE design tools

Completed research projects

• PLC2PAR - Programmable Logic Controller goes Parallel
  Funded by Software Offensive Bavaria, Information and Communication Technology; 1 November 2013 - 31 January 2017 - Prof. Jürgen Bäsig

  With the help of an evolutionary algorithm, optimal configurations for a special processor architecture are generated. These architectures have to be verified and validated from various standpoints. The Universal Verification Methodology (UVM) was used to verify this research project. Verification was carried out using selected pipeline stages based on deterministic data sets and simulated functions. Lastly, the entire system was verified and validated. Challenges were encountered in the form of generically implementing suitable coverage with a reusable test environment and generating randomized command sequences.

 Publications

• Kohl, Johannes; Bauer, Wolfgang; Bäsig, Jürgen; Fey, Dietmar: “Evaluating a Simulation based PLC Processor Optimization”. In: The Industrial Simulation Conferences Page (ISC) (Accepted), Warsaw, Poland, 2017
• Kohl, Johannes; Bauer, Wolfgang; Bäsig, Jürgen; Rübesam, Stefan; Fey, Dietmar: “Processor Error Detection Capabilities of Random Programs”. In: GI/GMM/ITG (organizer): TuZ 2017 conference record (Test methods and reliability of circuits and systems), Lübeck, Germany, vol. 29, 2017, pp 65-68.
• Kohl, Johannes; Bauer, Wolfgang; Bäsig, Jürgen; Rübesam, Stefan; Fey, Dietmar: “Generation of Executable Runtime Constrained Random Programs Functional Processor Verification”. In: eurosis (organizer): ESM 2016 (The European Simulation and Modelling Conferences), Gran Canaria, Spain, Vol. 30, 2016, pp 256-263.
• Bauer, Wolfgang ; Bäsig, Jürgen: “Verification of specific processor pipeline stages with UVM”. Lecture User2User, Mentor User Conference, Mentor Graphics, Munich, 15/10/2015.

Laboratory management

Prof. Jürgen Bäsig

Laboratory staff

Detlef Hinz-Hemmers (Dipl.-Ing. (FH))